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Designed by
GlobalAMS
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| The 8255A is a
programmable peripheral interface (PPI) device designed for use
in Intel microcomputer systems. Its function is that of a
general purposes I/O component to Interface peripheral equipment
to the microcomputer system bush. The functional configuration
of the 8255A is programmed by the systems software so that
normally no external logic is necessary to interface peripheral
devices or structures. |
| This 3-stable
bi-directional 8-bit buffer is used to interface the 8255A to
the systems data bus. Data is transmitted or received by the
buffer upon execution of input or output instructions by the
CPU. Control words and status information are also transferred
through the data bus buffer. |
Read/Write and Control Logic
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| The function of this block
is to manage all of the Internal and External transfers of both
Data and Control or Status words. It accepts inputs from the CPU
Address and Control business and in turn, issues commands to
both of the Control Groups. |
|
(CS)
Chip Select. A
“low’ on this input pin enables the communication between
the 8255A, and the CPU.
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(RD)
Read. A “low” on
this Input pin enables the 8255A to send the data or status
information to the CPU on the data bus. In essence, it allows
the CPU to “read from the 8255A.
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(WR)
Write. A. “ low”
on the input pin enables the CPU to write data or control words
into the 8255A.
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| Port Select 0 and Port
Select 1. The Input signals, in conjunction with the RD and WR
Inputs, controls the selection of one of the three ports or the
control word registers. They are normally connected to the least
significant bits of the address bus (A0 and A1). |
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A1
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A0
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___
RD
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___
WR
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___
CS
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INPUT
OPERATION (READ)
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0
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0
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0
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1
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0
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PORT
A – DATA BUS
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0
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1
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0
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1
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0
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PORT
B – DATA BUS
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1
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0
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0
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1
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0
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PORT
C – DATA BUS
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OUTPUT
OPERATION (WRITE)
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0
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0
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1
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0
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0
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DATA
BUS – PORT A
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0
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1
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1
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0
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0
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DATA
BUS -- PORT B
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1
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0
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1
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0
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0
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DATA
BUS – PORT C
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1
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1
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1
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0
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0
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DATA
BUS – CONTROL
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DISABLE
FUNCTION
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X
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X
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X
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X
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1
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DATA
BUS – 3 STATE
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1
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1
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0
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1
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0
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ILLEGAL
CONDITION
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X
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X
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1
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1
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0
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DATA
BUS – 3 STATE
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Figure 3.
8255 A Block Diagram Showing Data Bus Buffer and Read/Write
Control Logic Functions
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(RESET)
Reset. A
“high” on this Input clears the control register and all
ports (A, B, C) are set to the Input mode.
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Group A and Group B Controls
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The functional
configuration of each port is programmed by the systems
software. In essence, the CPU “output” a control word to the
8255A. The control word contains information such as “mode”,
bit set”, bit reset”, etc. that Initializes the functional
configuration of the 8255A.
Each of the
Control blocks (Group A and Group B) accepts commands from the
Read/Write Control Logic, receives control words from the
internal data bus and issues the proper commands to its
associated ports.
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Control Group A – Port A and Port C upper (C7 C4)
Control Group B – Port B
and Port C lower (C3 C0)
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The Control Word
Register can only be written into. No.
Read operation of the
Control Word Register is allowed.
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| The 8255A contains three
8-bit ports (A , B, and C). All
can be configured in a wide variety of
functional characteristics by the system software but
each has its own special features or personally to further
enhance the power and flexibility of the 8255A. |
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Port A.
One 8 bit data output latch/buffer and one 8-bit data input
latch.
Port B. One
8-bit data output latch/buffer and one 8-bit data input buffer.
Port C.
One 8-bit data output latch/buffer and one 8-bit data input
buffer (no latch for input). This port can be divided into two
4-bit ports under the mode control. Each 4-bit port contains a
4-bit latch and it can be used for the controls signal outputs
and status signal inputs in conjunction with ports A and B.
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D7 – D0
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DATA BUS DIRECTIONAL
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RESET
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RESET INPUT
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CS
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CHIP SELECT
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RD
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READ INPUT
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WR
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WRITE INPUT
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A0 – A1
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PORT ADDRESS
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PA 7 PA 0
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PORT A (BIT)
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PB 7 PB 0
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PORT B (BIT)
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PC 7 PC 0
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PORT C (BIT)
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Vcc
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5 VOLTS
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GND
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0 VOLTS
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8255A OPERATIONAL DESCRIPTION
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| There are three basic modes
of operation that can be selected by the systems software: |
|
Mode O – Basic Input/Output
Mode 1 – Strobed
Input/Output
Mode 2 – Bi-Directional
Bus
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When the reset Input
goes “high” all ports will be set to the Input mode (i.e.,
all 24 lines will be in the high Impedance state). After the
reset is removed the 8255A can remain in the input mode with no
additional Initialization required. During the execution of the
systems program any of the other modes may be selected using a
single output Instruction. This allows a single 8255A to service
a variety of peripheral devices with a simple software
maintenance routine.
The modes for
Ports A and Port B can be separately defined, while Port C is
divided into two portions as required by the Port A and Port B
definitions. All of the output registers, including the status
flip-flops, will be reset whenever the mode is changed. Modes
may be combined so that their functional definition can be
“tailored” to almost any
I/O stricture. For instance; Group B can be programmed in Mode 0
to monitor simple switch closing or display computational
results, Group A could be programmed in Mode 1 to monitor a
keyboard or tape reader on an interrupt-driven basis.
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Figure 6. Mode
Definition Format
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| The
Mode definitions and possible mode combinations may seem
confusing at first but after a cursory review of the complete
device operation a simple , logical I/O approach will surface.
The design of the 8255A has taken into account things such as
efficient PC board layout, control signal definition vs
PC layout and complete functional flexibility to support
almost any peripheral device with no use of the available pints. |
Single Bit Set/Reset Feature
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| Any of the eight bits of
Port C can be Set or Reset using a single OUT put Instruction.
This feature reduces software requirements in Control-based
applications. |
| When Port C is being used
as status/control for Port A or B these Bits can be set or reset
by using the Bit set/reset operation just as if they were data
output port. |
Interrupt Control Functions
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| When the 8255A is
programmed to operate in mode 1 or mode 2, control signals are
provided that can used as interrupt request input to the CPU.
The interrupt request signal generated from port C, can be
inhibited or enabled by setting or resetting the associated INTE
flip-flop, using the bit set/reset function of port C. |
| This function allows the
Programmer to disallow or allow a specific I/O device to
interrupt the CPU without affecting any other device in the
interrupt structure. |
INTE
flip-flop definition
(BIT-SET) – INTE
is SET – Interrupt enable
(BIT-RESET) –
INTE is RESET – Interrupt disable
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| Note: All Mask flip-flops
are automatically reset during mode selection and device reset. |
| Mode 0 (Basic
Input/Output). This functional
configuration provides simple input operations for each of the
three ports. No “handshaking”
is required data is simply written to or read from a
specified port.
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| Mode O Basic Functional
Definitions: |
- Two
8-bit ports and two 4-bit port
- Any
port can be input or output.
- Outputs
are not latched.
- Inputs
are not latched.
- 16
different Input/output configurations are not possible in this
Mode.
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A
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B
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GROUP
A
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GROUP
B
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D4
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D3
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D2
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D1
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PORT
A
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PORT
C
(UPPER)
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#
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PORT
B
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PORT
C
(LOWER)
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0
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0
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0
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0
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OUTPUT
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OUTPUT
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0
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OUTPUT
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OUTPUT
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0
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0
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0
|
1
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OUTPUT
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OUTPUT
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1
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OUTPUT
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INPUT
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0
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0
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1
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0
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OUTPUT
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OUTPUT
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2
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INPUT
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OUTPUT
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0
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